DBus hardware access - From TI view (registers)

DBus hardware access (TI9x only)

Well, the whole doc is focused on link from a PC view. This topic add a TI view.
While I was working on TiEmu II, I had to fix linkport support which was quite broken. Unfortunately, I didn't know very much about how linkport works on TI side. This was quite annoying. Then, I decided to dis-assemble low-level linkport routines and the result of this work is below.

1°) DBus registers in $600000 ports

Informations below comes from Johan Eilert's j89hw.txt documentation and TI's TI89/TI92 Plus Developper Guide:

DBus Control & Status
Control ($60000C)
 Status ($60000D)
15
 14
 13
 12
 11
 10
 9
 8
 7
 6
 5
 4
 3
 2
 1
 0
AE
 LD
 LTO
CLE
 CA
 CTX
 CRX
 SLE
 STX
 SRX
 SLI
 SA
 EA?


Control:
AE
 Autostart Enable
 Bit set and bit 3 of $600005 set : wake-up calc on Dbus activity.
LD
 Link Disable
 Set it to 1 when you want to use direct access to register $60000E. Disable byte sender/receiver.
LTO
 Link Time-out Disable
 Disable link time-out (red/white are low for more than 2 seconds).



CLE
 Link Error Interrupt Enable
 Allow SLE to trigger interrupt.
CA
 AutoStart Interrupt Enable Allow SA to trigger interrupt.
CTX
 TX buffer empty Interrupt Enable Allow STX to trigger interrupt (and triggers interrupt immediately given that STX is usually set).
CRX
 RX buffer full Interrupt Enable Allow SRX to trigger interrupt.

Status:
SLE
 Link Error
 Dbus error (timing or protocol violation).
STX
 TX buffer empty
 Transmit buffer is empty.
SRX
 RX buffer full
 Receive buffer is empty.
SLI
 Link Interrupt
 Never used (at least in TI AMS). SLI = SLE | STX | SRX | SA.
SA
 AutoStart
 Link activity on DBus port.
EA ?
 External Activity ?
 External activity (DBus lines are toggling). Used by AMS >= 2.08


Always 1.


Always 0.
Warning: reading this register resets it ! Take care to read it once and store its value for subsequent operations.
Warning2: this is what TI says in their SDK but I'm not sure that's true (at least in TiEmu).

DBus Direct & Data
Direct ($60000E)
 Data ($60000F)
15
 14
 13
 12
 11
 10
 9
 8
 7
 6
 5
 4
 3
 2
 1
 0




D1I
(white)
 D0I
(red)
 D1O
 D0O
 RX/TX 1-byte buffer

Direct access:
D1I
 D1 input
 Live status of D1/ring/white  (1=pulled down).
D0I
 D0 input
 Live status of D0/tip/red  (1=pulled down).
D1O
 D1 output
 Activate (pull down) D1/ring/white.
D0O
 D0 output
 Activate (pull down) D1/ring/white.

2°) Link behaviour

The link is interrupt-driven and relies on 2 circular buffers of 128 bytes each. Each buffer is managed as a stucture.
In normal operating mode, AE, CLE, CA and CRX are enabled. CTX is set in the transmit routine. It is disabled at the end of the handler when no more chars have to be transmitted.

Some informations comes from dis-assembling, some others comes from TIGCC documentation (after check-up).

* AI4 handler : it begins by checking some flags in the control register:
- SA=1 => exit,
- SLE=1 => reset link port ($E0, $8D in ctrl reg),
- SRX=1 => receive char from rx/tx register and put it in circular buffer,
AMS < 2.08:
- STX=1 => transmit char from circular buffer (please note this step is blocking),
AMS >= 2.08: (AMS208 add a bit check before entering into tx routine).
- EA = 0 => exit,
- STX=1 => transmit char.


* OSLinkReset : OSLinkReset resets the link interface. It also resets all link variables and performs OSLinkClose. Ints are disabled during call.

* OSLinkOpen : OSLinkOpen clears both transmit and receive queues, then set a flag which tells that the communication is opened.

* OSLinkClose : OSLinkClose waits until eventual bytes waiting in transmit queue are sent out, then clears both transmit and receive queues, and clear a flag which tells that the communication is opened. Ints are disabled during call.

* OSLinkTxQueueInquire : OSLinkTxQueueInquire returns the number of free bytes in the link transmit buffer. Ints are disabled during call.

* OSLinkTxQueueActive : OSLinkTxQueueActive returns TRUE if the transmit queue is active, else returns FALSE. This function checks CTX bit. Ints are disabled during call.

* OSWriteLinkBlock : inserts num bytes from buffer into the link transmit buffer. Returns 0 if the operation was sucessful, else returns a non-zero value. num must be in the range 1-128. Ints are disabled during call.
Note: the routine enables TX interrupt by setting the CTX bit. Consequently, the AI4 handler will be called as soon as ints (SR) will be enabled given that STX is set.
 
* OSCheckSilentLink : OSCheckSilentLink returns an integer which determines the link state..

* OSLinkCmd : to do...

Dis-assembled output: here. The output contains comments only. I can put source code, this is strictly forbidden by TI. I will not distribute it, neither here, nor by mail.

3°) Remarks

Sending 4 bytes on the linkport sets the followinf flags : TRIA TRIA TRIA TRI TI ( T = STX, R = SRX, I = SLI and A = EA).

More Information

You may find some informations in the TIGCC documentation.

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